<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<OPBytesBlocks>
	<OPBytesBlock baseAddress="0x40022028" length="44" RegType="OptionBytes"/>
</OPBytesBlocks>
<OPBytes baseAddress="0x40022028" length="44" RegType="OptionBytes">
	<OPByte>
		<name>FMC_OBCTL</name>
		<displayName>FMC_OBCTL</displayName>
		<addressOffset>0x0</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0xFF1F9FA5</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>DCACHE_ECCEN</name>
				<brief>enable DCACHE ECC</brief>
				<description>enable DCACHE ECC&#x000A;0: disable DCACHE ECC&#x000A;1: enable DCACHE ECC</description>
				<bitOffset>26</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>ICACHE_ECCEN</name>
				<brief>enable ICACHE ECC</brief>
				<description>enable ICACHE ECC&#x000A;0: disable ICACHE ECC&#x000A;1: enable ICACHE ECC</description>
				<bitOffset>25</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>SRAM_RST</name>
				<brief>sram initialize</brief>
				<description>sram initialize&#x000A;0: Initialize SRAM after power reset&#x000A;1: Do not initialize SRAM after power reset</description>
				<bitOffset>24</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>BOREF_TH</name>
				<brief>BOR eflash threshold</brief>
				<description>BOR eflash threshold&#x000A;000: 1.61V rising threshold, 1.57V falling threshold&#x000A;001: 1.66V rising threshold, 1.62V falling threshold&#x000A;010: 1.71V rising threshold, 1.67V falling threshold&#x000A;011: 1.76V rising threshold, 1.72V falling threshold&#x000A;100: 1.81V rising threshold, 1.77V falling threshold&#x000A;101~111: 1.86V rising threshold, 1.82V falling threshold</description>
				<bitOffset>21</bitOffset>
				<bitWidth>3</bitWidth>
			</field>
			<field>
				<name>FWDGSPD_STDBY</name>
				<brief>FWDGT suspend option in standby mode configuration</brief>
				<description>FWDGT suspend option in standby mode configuration&#x000A;0: FWDGT is suspend in system standby mode&#x000A;1: FWDGT is running in system standby mode</description>
				<bitOffset>20</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>FWDGSPD_DPSLP</name>
				<brief>FWDGT suspend option in deepsleep mode configuration</brief>
				<description>FWDGT suspend option in deepsleep mode configuration&#x000A;0: FWDGT is suspend in system deepsleep mode&#x000A;1: FWDGT is running in system deepsleep mode.</description>
				<bitOffset>19</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>nBOOT0</name>
				<brief>Boot0 configuration bit</brief>
				<description>Boot0 configuration bit&#x000A;0: BOOT0 is 1&#x000A;1: BOOT0 is 0</description>
				<bitOffset>18</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>nBOOT1</name>
				<brief>Boot1 configuration bit</brief>
				<description>Boot1 configuration bit&#x000A;0: BOOT1 is 1&#x000A;1: BOOT1 is 0&#x000A;Together with the BOOT0 pin, this bit selects boot mode</description>
				<bitOffset>17</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>nSWBT0</name>
				<brief>Software BOOT0 disable</brief>
				<description>Software BOOT0 disable&#x000A;0: BOOT0 depends on the option bit nBOOT0&#x000A;1: BOOT0 depends on PB8/BOOT0 pin</description>
				<bitOffset>16</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>BOR_TH</name>
				<brief>BOR_TH Level Selection</brief>
				<description>BOR_TH Level Selection&#x000A;000: 3.0V rising threshold, 2.9V falling threshold&#x000A;001: 2.9V rising threshold, 2.8V falling threshold&#x000A;010: 2.7V rising threshold, 2.6V falling threshold&#x000A;011: 2.6V rising threshold, 2.5V falling threshold&#x000A;100: 2.5V rising threshold, 2.4V falling threshold&#x000A;101: 2.3V rising threshold, 2.2V falling threshold&#x000A;110: 2.1V rising threshold, 2.0V falling threshold&#x000A;111: 1.85V rising threshold, 1.75V falling threshold</description>
				<bitOffset>13</bitOffset>
				<bitWidth>3</bitWidth>
			</field>
			<field>
				<name>BOR_EN</name>
				<brief>BOR_EN</brief>
				<description>BOR_EN&#x000A;0: BOR enable&#x000A;1: BOR disable</description>
				<bitOffset>12</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>SRAM_ECCEN</name>
				<brief>SRAM ECC disable</brief>
				<description>SRAM ECC disable&#x000A;0: SRAM ECC enable&#x000A;1: SRAM ECC disable</description>
				<bitOffset>11</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>nRST_STDBY</name>
				<brief>Option byte standby reset value</brief>
				<description>Option byte standby reset value&#x000A;0: Generates a reset if entering standby mode&#x000A;1: No reset if entering standby mode</description>
				<bitOffset>10</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>nRST_DPSLP</name>
				<brief>Option byte deepsleep reset value</brief>
				<description>Option byte deepsleep reset value&#x000A;0: Generates a reset if entering Deep-sleep mode&#x000A;1: No reset if entering Deep-sleep mode</description>
				<bitOffset>9</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>nFWDG_HW</name>
				<brief>Free watchdog configuration bit</brief>
				<description>Free watchdog configuration bit&#x000A;0: Hardware free watchdog&#x000A;1: Software free watchdog</description>
				<bitOffset>8</bitOffset>
				<bitWidth>1</bitWidth>
			</field>
			<field>
				<name>SPC[7:0]</name>
				<brief>Option byte security protection value</brief>
				<description>Store SPC of option bytes block after system reset.</description>
				<bitOffset>0</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_SCRWLK</name>
		<displayName>FMC_SCRWLK</displayName>
		<addressOffset>0x4</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0x0000FFFF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>SCRWLK[15:0]</name>
				<brief>Enable SCR write lock</brief>
				<description>Enable SCR write lock</description>
				<bitOffset>0</bitOffset>
				<bitWidth>16</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_WP_0</name>
		<displayName>FMC_WP_0</displayName>
		<addressOffset>0x8</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0x000000FF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>WP0_EADDR[7:0]</name>
				<brief>WP area end page</brief>
				<description>WP area end page</description>
				<bitOffset>16</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
			<field>
				<name>WP0_SADDR[7:0]</name>
				<brief>WP area start page</brief>
				<description>WP area start page</description>
				<bitOffset>0</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_WP_1</name>
		<displayName>FMC_WP_1</displayName>
		<addressOffset>0xC</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0x000000FF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>WP1_EADDR[7:0]</name>
				<brief>WP area end page</brief>
				<description>WP area end page</description>
				<bitOffset>16</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
			<field>
				<name>WP1_SADDR[7:0]</name>
				<brief>WP area start page</brief>
				<description>WP area start page</description>
				<bitOffset>0</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_WP_2</name>
		<displayName>FMC_WP_2</displayName>
		<addressOffset>0x10</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0x000000FF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>WP2_EADDR[7:0]</name>
				<brief>WP area end page</brief>
				<description>WP area end page</description>
				<bitOffset>16</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
			<field>
				<name>WP2_SADDR[7:0]</name>
				<brief>WP area start page</brief>
				<description>WP area start page</description>
				<bitOffset>0</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_WP_3</name>
		<displayName>FMC_WP_3</displayName>
		<addressOffset>0x14</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0x000000FF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>WP3_EADDR[7:0]</name>
				<brief>WP area end page</brief>
				<description>WP area end page</description>
				<bitOffset>16</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
			<field>
				<name>WP3_SADDR[7:0]</name>
				<brief>WP area start page</brief>
				<description>WP area start page</description>
				<bitOffset>0</bitOffset>
				<bitWidth>8</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_OTPDATA1_LLK</name>
		<displayName>FMC_OTPDATA1_LLK</displayName>
		<addressOffset>0x1C</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0xFFFFFFFF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>OTPDATA1_LWLK[31:0]</name>
				<brief>OTP USER_DATA1 block write lock</brief>
				<description>OTP USER_DATA1 block write lock</description>
				<bitOffset>0</bitOffset>
				<bitWidth>32</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_OTPDATA1_HLK</name>
		<displayName>FMC_OTPDATA1_HLK</displayName>
		<addressOffset>0x20</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0xFFFFFFFF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>OTPDATA1_HWLK[63:32]</name>
				<brief>OTP DATA1 block write lock</brief>
				<description>OTP DATA1 block write lock</description>
				<bitOffset>0</bitOffset>
				<bitWidth>32</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_OTPDATA2_LLK</name>
		<displayName>FMC_OTPDATA2_LLK</displayName>
		<addressOffset>0x24</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0xFFFFFFFF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>OTPDATA2_LWLK[31:0]</name>
				<brief>OTP USER_DATA2 block write lock</brief>
				<description>OTP USER_DATA2 block write lock</description>
				<bitOffset>0</bitOffset>
				<bitWidth>32</bitWidth>
			</field>
		</fields>
	</OPByte>
	<OPByte>
		<name>FMC_OTPDATA2_HLK</name>
		<displayName>FMC_OTPDATA2_HLK</displayName>
		<addressOffset>0x28</addressOffset>
		<size>0x20</size>
		<access>read-write</access>
		<reset>0xFFFFFFFF</reset>
		<complement>FFFF</complement>
		<fields>
			<field>
				<name>OTPDATA2_HWLK[63:32]</name>
				<brief>OTP USER_DATA2 block write lock</brief>
				<description>OTP USER_DATA2 block write lock</description>
				<bitOffset>0</bitOffset>
				<bitWidth>32</bitWidth>
			</field>
		</fields>
	</OPByte>
</OPBytes>
<OTPBytesBlocks>
    <OTPBlocks baseAddress="0x1FFF6800" length="4096"/>
</OTPBytesBlocks>
<OTPBytes baseAddress="0x1FFF6800" length="4096">
    <OTPBlocks>
        <name>OTP</name>
		<displayName>OTP</displayName>
        <minProgrammeWidth>0x80</minProgrammeWidth>
		<maxProgrammeWidth>0x80</maxProgrammeWidth>
		<eccsupport>128</eccsupport>
		<lockBaseAddress>0x0</lockBaseAddress>
		<BlockCnt>0x01</BlockCnt>
		<baseAddress>0x1FFF6800</baseAddress>
		<endAddress>0x1FFF77FF</endAddress>
        <fields>
		   <field>
                <name>OTP_Block</name>
				<displayName>OTP_Block</displayName>
                <baseAddress>0x1FFF6800</baseAddress>
		        <endAddress>0x1FFF77FF</endAddress>	
				<ifHasLockArea>0x0</ifHasLockArea>
				<size>0x1000</size>
				<lockOffset>0x00</lockOffset>
				<lockbitWidth>0</lockbitWidth>
				<LockVal>0</LockVal>
            </field>
        </fields>
    </OTPBlocks>
</OTPBytes>